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Cadence And GLOBALFOUNDRIES Announce First Test Chip Featuring ARM Cortex-A12 Processor In 28nm-SLP Process
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Cadence And GLOBALFOUNDRIES Announce First Test Chip Featuring ARM Cortex-A12 Processor In 28nm-SLP Process  
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Friday, March 21, 2014 At CDNLive Silicon Valley 2014, Cadence Design Systems Inc. (NASDAQ: CDNS) and GLOBALFOUNDRIES announced that they have taped out a quad core test chip built around the ARM Cortex-A12 processor. Targeted to operate at frequencies of up to 2.0GHz while still within the mainstream mobile power and area envelope, the test chip is implemented in GLOBALFOUNDRIES' 28nm-SLP (Super Low Power 28 nanometer High-K Metal Gate) process using a full Cadence® tool flow and incorporates ARM POP™ technology to leverage the full performance range of the 28-SLP process.

The Cortex-A12 processor provides a 40 percent performance increase and direct upgrade path from ARM's highly successful Cortex-A9 processor, while matching the energy efficiency of its predecessor. The successful tapeout marks an important move toward the incorporation of the Cortex-A12 core in mobile applications such as smartphones and tablets.

"As the lead foundry working with the Cortex-A12 processor, we collaborated closely with Cadence and ARM to implement this new core using our 28nm low-power process, and ARM libraries specifically tuned to meet demanding mobile market requirements," said Ana Hunter, vice president of product management at GLOBALFOUNDRIES. "This test chip will be instrumental in showing our mutual customers how they can productize and reap the benefits from the Cortex-A12 processor in conjunction with the 28nm-SLP process using a Cadence flow."

"The ARM Cortex-A12 processor is a high-performance compute solution that will benefit developers looking to upgrade existing mid-range mobile products as well as expanding our technology into a new range of electronic devices such as set-top boxes," said Dipesh Patel, executive vice president and general manager, physical design group, ARM. "The work by ARM, Cadence and GLOBALFOUNDRIES in jointly developing a test chip on 28nm utilizing ARM POP IP will accelerate its time to market."

The full Cadence RTL-to-signoff digital implementation flow was used, including Encounter® RTL Compiler, Encounter RTL Compiler with Physical, Encounter Digital Implementation System and Encounter Conformal Equivalence Checker. The full suite of Cadence signoff tools were also used, including QRC Extraction, Tempus™ Timing Signoff Solution and the Physical Verification System, closing final signoff and achieving tapeout in 15 weeks from RTL availability.

"Projects like this Cortex-A12 processor test chip are important milestones, and can only be achieved through tight collaboration," said Anirudh Devgan, senior vice president of the Digital and Signoff Group at Cadence. "Our work with GLOBALFOUNDRIES and ARM will be welcome news for electronics companies interested in exploring ARM's newest core."

GLOBALFOUNDRIES' 28nm-SLP technology is ideally suited for the next generation of smart mobile devices, enabling designs with faster processing speeds, smaller feature sizes, lower standby power and longer battery life. The technology is based on GLOBALFOUNDRIES' "Gate First" approach to High-K Metal Gate (HKMG), which has been in volume production for nearly three years. The technology offers a combination of performance, power efficiency and cost that is ideally suited for the mobile market.

POP technology contains ARM Artisan® Physical IP logic libraries and memory instances specifically tuned for a given ARM core and process technology, a comprehensive benchmarking report to pinpoint exact conditions and results ARM achieved for core implementation, and POP implementation knowledge including a user guide, floor plans and scripts. POP IP products are currently available from 40nm to 28nm, with a roadmap down to 14nm process technology for a wide range of Cortex-A processor series CPU and Mali™ GPU products.

GLOBALFOUNDRIES will deliver a presentation on their joint work at CDNLive Silicon Valley today, March 12. The presentation is titled, "A Power-, Performance-, and Cost-Optimized Cortex-A12 Implementation in 28nm-SLP (Super-Low-Power) Technology"

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