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Cadence Successfully Concludes Its Annual Flagship Conference CDNLive India 2014
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Cadence Successfully Concludes Its Annual Flagship Conference CDNLive India 2014  
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Saturday, August 16, 2014 Cadence Design Systems (India) Pvt. Ltd., a subsidiary of Cadence (NASDAQ: CDNS), successfully concluded its annual flagship conference CDNLive India 2014. This year, the conference brought together users and industry experts from semiconductor, electronics product and design services companies and featured keynotes from ARM India and Wipro Technologies. The winners of CDNLive India 2014 Best Paper Awards were also announced.

The two-day conference, held on August 12 and 13, provided an opportunity for delegates to network with peers, share best practices, understand the latest solutions and discover new techniques to address their most difficult design challenges.

Speaking about the conference, Jaswinder Ahuja, corporate vice president and managing director of Cadence Design Systems (India) Pvt. Ltd., said, “CDNLive India provides an excellent platform to our customers and partners to exchange ideas, network, share best practices and learn new ways to address their specific design challenges. The attendees, paper submissions and discussions reflect the breadth of expertise in and the growth of the electronics design community in India.”

On Day 1, August 12, Lip-Bu Tan, president & CEO, Cadence Design Systems, Inc., gave a keynote address on “Innovation in System of Systems” followed by Guru Ganesan, president and managing director, ARM India. On Day 2, August 13, Charlie Huang, senior vice president, Worldwide Field Operations and System & Verification Group and Vasudevan Aghoramoorthy, vice president - PES, Wipro Technologies addressed the audience.

The conference featured 9 tracks, 79 paper presentations, 10 technology update presentations, 2 panel discussions in the digital implementation and mixed-signal design tracks, a design IP breakout session, technology pods on the latest Cadence technologies and an exhibition area with booths by Cadence partners and customers.

Companies such as AMD, Analog Devices, Broadcom, Calibre Interconnect Solutions, Cisco, eInfochips, Ericsson, Freescale, IBM, Megachips Corporation, MindTree, Open-Silicon, PMC-Sierra, Qualcomm, RCI, Samsung, Sankalp Semiconductor, Sanmina Technology, Tejas Networks, Texas Instruments and Wipro Technologies presented papers.

The best paper award winners were:


Digital Implementation & Signoff I - Open-Silicon - Macro Clustering Based Power Planning And Switch Cell Insertion

Digital Implementation & Signoff II - Open-Silicon - Know Thy Ropes - For Accelerated Timing Constraint Analysis, Refinement And Validation Within The Realms Of ETS And CCD

Front-End Design - Texas Instruments - Techniques For ATPG QOR Improvement For An Extensive X-Source Design

Custom & Analog Design - Texas Instruments - Compiler Memory Characterization Using Liberate-MX And XPS To Achieve Increased Accuracy With Improved Run Time

Mixed-Signal Design - Texas Instruments - Surprise Or Shock? Transistor Level Functional Analysis Of Digital Circuits And Systems Are Still Needed!

System Design & Verification I - PMC-Sierra - Exploiting The Best Of Verified Verification IP Using Multi Language Verification Environment.

System Design & Verification II - Open-Silicon - Developing A Power Optimized Interconnect For Optimum SOC Performance

PCB Design & IC Packaging - L&T Technology Services - Lead Time Reduction Of Probe Card/LTCC Layout Design Using Cadence Allegro

System Design & Verification III (HW) - Texas Instruments - Enabling Packaging And Software Optimizations For Low-Power Designs By Pre-Silicon Power Analysis Of SOC Use-Case Using Cadence Palladium DPA Flow

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