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Wednesday, October 07, 2015

Samsung Achieves 14-nm FinFET Tapeout
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Samsung Achieves 14-nm FinFET Tapeout  
The new test chip on Samsung's 14LPE process marks the result of collboration between Samsung and Synopsys over FinFET technology.   
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Friday, December 21, 2012 Samsung has successfully achieved the tapeout of the first test chip on its 14LPE process. The tapeout is a result of the collaboration between Samsung and Synopsys over FinFET technology. The collaboration aims to deliver foundation modeling technologies for 3D parasitic extraction, circuit simulation and physical design-rule support of FinFET devices. Synopsys' solution for embedded memory, physical design, parasitic extraction, timing analysis and signoff is built on this foundation.

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Dr. Kyu-Myung Choi, VP, System LSI infrastructure design center, Device Solutions, Samsung Electronics said, "FinFET transistors can deliver lower power consumption and higher device performance, but they also bring tough challenges. We chose Synopsys as our FinFET collaboration partner to solve these challenges, because of our successful history together at 20 nanometer and other nodes. We continue to pool our expertise to deliver innovative FinFET solutions."

Synopsys and Samsung have worked together to develop the test chip that validates Samsung's 14-nm process as well as Synopsys DesignWare Embedded Memories using Synopsys' Self-Test and Repair (STAR) Memory System solution. The test chip will enable the correlation of the simulation models to the FinFET process and contains test structures, standard cells, a PLL and embedded SRAMs. The memory instances include high-density SRAMs designed to operate at very low voltages and high-speed SRAMs to validate the process performance.

Antun Domic, senior VP and GM, Implementation Group, Synopsys said, "Samsung is a key partner in our effort and investment to develop a complete solution for FinFET technology. Synopsys' extensive collaboration with Samsung enables us to deliver best-in-class technologies and IP to help designers realize the full potential of FinFET transistor designs."

Srinivas Nallani  Chakravathi, EFYTIMES News Network

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