SRAM chips are precursors to more complex devices such as microprocessors. The SRAM cell utilises a conventional six-transistor design and has an area of 0.1um2, breaking the previous SRAM scaling barriers.
"We are working at the ultimate edge of what is possible -- progressing toward advanced, next-generation semiconductor technologies," said Dr T.C. Chen, vice president, Science and Technology, IBM Research. "This new development is a critical achievement in the pursuit to continually drive miniaturisation in microelectronics."
According to the company, 22nm is two generations away in chip manufacturing. The next generation is 32nm -- where IBM and its partners are in development with their leading 32nm high-K metal gate technology that no other company or consortium can match.
Traditionally, an SRAM chip is made more dense by shrinking its basic building block, often referred to as a cell. IBM-alliance researchers optimised the SRAM cell design and circuit layout to improve stability and developed several novel fabrication processes in order to make the new SRAM cell possible. The researchers utilised high-NA immersion lithography to print the aggressive pattern dimensions and densities and fabricated the parts in its 300mm semiconductor research environment.
Key enablers of the SRAM cell include band edge high-K metal gate stacks, transistors with less than 25nm gate lengths, thin spacers, novel co-implants, advanced activation techniques, extremely thin silicide and damascene copper contacts. |
